1. Field of the Invention
The present invention relates to a reference voltage selecting circuit of a semiconductor memory device; and more particularly, to a circuit and a method for selecting reference voltage in a semiconductor memory device, in which an internal voltage and/or high voltage can be changed using a plurality of reference voltage generators and circuitry to select different reference voltage combinations in a semiconductor memory device.
2. Prior Art of the Invention
Recent semiconductor memory devices use an internal voltage generating circuit for receiving an external voltage source and then generating an internal voltage lower than the exterior voltage source in order to get low voltage and low consumption of electric power. For instance, in a semiconductor memory device such as an EDO DRAM, the internal voltage generating circuit serves a role of dropping a 3.3V external voltage source to a 2.8V internal voltage source.
In such semiconductor memory devices, the internal voltage generating circuit drops the voltage level of an external power supply to a lower voltage level for use as an internal power supply. The internal voltage generating circuit not only ensures that a stabilized power supply voltage is presented to the chip internal circuits when the external voltage source fluctuates, but also actively responds to temperature or processing condition fluctuations, thereby guaranteeing constant chip performance.
FIG. 1 is a block diagram of a conventional semiconductor memory device showing a connection relation among voltage generators for generating an internal voltage and a high voltage.
A reference voltage generator 10 receives an external voltage (EVC), generates a given reference voltage VREF, and applies it to an internal voltage generator 12. The internal voltage generator 12 receives reference voltage VREF, generates an internal voltage (IVC) having a constant level, and applies it to a memory cell array area or to a peripheral area. A high voltage generator 14 receives and boosts reference voltage VREF, generates a high voltage VPP having a given level, and applies it as a word line gate voltage. When the high voltage VPP is increased, current consumption and speed increase. Conversely, when the high voltage VPP is decreased, current consumption and speed decrease.
In such semiconductor memory devices, in order to execute a memory cell test, promote the speed of the semiconductor memory device, or lessen current consumption, the internal voltage source IVC or high voltage VPP voltage level should be changed. To change the internal voltage or the high voltage, the reference voltage VREF should be changed.
In such semiconductor memory devices, however, since the reference voltage VREF output from the reference voltage generator 10 is used in common to generate the internal voltage IVC and the high voltage VPP, the internal voltage IVC or the high voltage VPP cannot be changed to perform the memory cell test, promote the speed of the semiconductor memory device, or reduce current consumption.
Since the reference voltage VREF for internal voltage IVC and high voltage VPP are the same, the internal voltage IVC and the high voltage VPP are generated in an interlocking state, making it is impossible to separately change the internal voltage source IVC and the high voltage VPP.